To divide and display the time course of a video signal in an optimum form by continuously arranging a video signal in an image memory in a reduced small image state, selecting reduced small images for one frame from the image memory of plural frames and rearranging and displaying them.

A record start signal is inputted to a trigger signal inputting means 107, an input signal from a video signal inputting means 101 is converted into digital image data by an A/D conversion circuit 102 and an image is reduced to 1/9 by a memory controlling means 103 and is recorded in an image memory 1 (104). A CPU 109 generates a memory switching signal. Small images that attach importance to the whole view are rearranged according to a parameter for display image generation in a ROM 110. Small images at the point of time of a trigger signal input are arranged around the screen center, as they approach around the screen center from the display start position, they are rearranged so that adjacent small image time interval can be from long the short and that a time interval up to a display end position can be from short to long.