Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
PRIORITY INTERRUPTION CIRCUIT
Document Type and Number:
Japanese Patent JPS5998257
Kind Code:
A
Abstract:

PURPOSE: To reduce the burden of software of a microprocessor, by determining precedence with hardware in the external of the microprocessor to be interrupted.

CONSTITUTION: An encoder circuit 8 discriminates the interruption of the highest priority of output lines P1"WP8" and outputs a 3-bit code signal 9 corresponding to this interruption and an intrruption request signal INT to a buffer circuit 10 and a microprocessor 1 respectively. When detecting the interruption request signal INT, the microprocessor 1 and its peripheral parts jump to each interruption program and set a bit in a reset port 4 through a data bus 3. Then, an interruption signal of a latch circuit 6 is reset to make it possible to accept the interruption again. The microprocessor 1 sets a mask port 5 in accordance with an executing program, thereby supplying only a non-masked interruption signal to the encoder circuit 8 through a gate circuit 7.


Inventors:
IMADA HIROSHI
Application Number:
JP20786182A
Publication Date:
June 06, 1984
Filing Date:
November 26, 1982
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
G06F9/48; (IPC1-7): G06F9/46
Attorney, Agent or Firm:
Yoshihiro Morimoto