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Patent Searching and Data


Title:
PROCESS SIMULATION DEVICE
Document Type and Number:
Japanese Patent JPH06105378
Kind Code:
A
Abstract:

PURPOSE: To simply implement test/debug of a built-up system dispensing with an actual hardware by operating an entry means or the like while observing an instrument installed flow diagram displayed on a display means of a system generating means so as to build up the system.

CONSTITUTION: The system requested by the user is built up by using a system generating means 1 while the system is displayed on a display means as an instrument installed flow diagram. The system consists of, e.g. an internal instrument having a function as a feedback regulator implementing PID control arithmetic operation, an internal instrument as a sequence regulator and an internal instrument having a switch function or the like. A process model simulating a controlled system by a process simulating means 2 is constituted in system to build up while displaying it on the display means as the instrument flow diagram. A test means 3 is activated when the built-up system is tested to connect the built-up system with the process model for the test. Thus, test/debug is implemented without using an actual controller (actual machine).


Inventors:
KENMOKU TSUTOMU
Application Number:
JP25322192A
Publication Date:
April 15, 1994
Filing Date:
September 22, 1992
Export Citation:
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Assignee:
YOKOGAWA ELECTRIC CORP
International Classes:
G05B23/02; G05B11/36; G06F19/00; H04Q9/00; (IPC1-7): H04Q9/00; G05B11/36; G05B23/02; G06F15/20
Attorney, Agent or Firm:
Shinsuke Ozawa