Title:
PROCESSING CIRCUIT OF PICTURE DATA
Document Type and Number:
Japanese Patent JPS58117068
Kind Code:
A
Abstract:
PURPOSE:To reduce the processing time remarkably. by processing picture data while fetching the picture data, through the use of a plurality of memories. CONSTITUTION:To a chip selector CS of a memory 3 and a write enable WE(D) during the timing T1, a data read/write clock signal (C) and a data write clock (D) are applied, and a picture data 1 is written to the memory 3 via a data-in terminal DI and no picture data is written in other memories 4, 5. In the timing period T2, the picture data 2 is written in the memory 4 only with the similar procedure, and in the timing period T3, the picture data 1, 2 already written in the memories 3, 4 are read out and the picture data 3 is written in the memory 5. Thus, while fetching picture data shared by three lines having different combination at all times, the picture data are inputted to a logical operation circuit 10 one by one bit sequentially for the logical operation of 3 (line number) X 3 (pickup cell number).
Inventors:
TANAKA ISAMU
Application Number:
JP21417181A
Publication Date:
July 12, 1983
Filing Date:
December 29, 1981
Export Citation:
Assignee:
SHIMADZU CORP
International Classes:
G06T1/60; G06F5/16; (IPC1-7): G06F15/20
Domestic Patent References:
| JPS53105945A | 1978-09-14 | |||
| JPS4857562A | 1973-08-13 |
Attorney, Agent or Firm:
Kazuhide Okada
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