Title:
多層半導体ウエハの処理
Document Type and Number:
Japanese Patent JP5453386
Kind Code:
B2
Abstract:
A method and apparatus for machining, or forming a feature in, a patterned silicon wafer includes removing portions of surface layers on the wafer using a first pulsed laser (4) beam with a pulse width between 1 ps and 1000 ps; and removing portions of bulk silicon (1) underlying the surface layers from the wafer using a second pulsed laser (5) beam with a wavelength between 200 nm and 1100 nm. Re-deposited silicon may be removed from the wafer by etching.
Inventors:
Rodin, Alexei
Boyle, Adrian
Brennan, Neil
Callahan, Joseph
Boyle, Adrian
Brennan, Neil
Callahan, Joseph
Application Number:
JP2011500175A
Publication Date:
March 26, 2014
Filing Date:
March 16, 2009
Export Citation:
Assignee:
Electro Scientific Industries, Inc.
International Classes:
B23K26/36; B23K26/00; B23K26/064; B23K26/382; H01L21/301; H01L21/3205; H01L21/768; H01L23/522
Domestic Patent References:
| JP2008522832A | ||||
| JP2005059042A | ||||
| JP2000263258A | ||||
| JP2007508946A | ||||
| JP4065154A |
Attorney, Agent or Firm:
Shoyo domestic and overseas patent office