Title:
PROCESSING SPEED MATCHING CIRCUIT AND MICROPROCESSOR
Document Type and Number:
Japanese Patent JP2022033968
Kind Code:
A
Abstract:
To provide a processing speed matching circuit and a microprocessor in which occurrence of malfunction of a program is suppressed even when the program including an instruction code of which processing speed is not consistent with processing speed of an arithmetic processing part is used.SOLUTION: The present invention comprises a detection part 12 acquiring an instruction code<1>included in a program from a storage device 30 storing the program for operating an arithmetic processing part 20, and detecting a specific instruction code to be predicted that mismatch occurs between the time required for processing the instruction code<1>and the processing speed of the arithmetic processing part 20, and a waiting part 16 making execution start of the specific instruction code wait only for the time corresponding to the mismatch if the specific instruction code is detected in the detection part 12.SELECTED DRAWING: Figure 1
Inventors:
YAMAZAKI HIROSHI
Application Number:
JP2021202559A
Publication Date:
March 02, 2022
Filing Date:
December 14, 2021
Export Citation:
Assignee:
LAPIS SEMICONDUCTOR CO LTD
International Classes:
G06F9/30
Domestic Patent References:
| JPS62174832A | 1987-07-31 | |||
| JP2000311061A | 2000-11-07 | |||
| JP2008071084A | 2008-03-27 |
Attorney, Agent or Firm:
Atsushi Nakajima
Kato Kazuho
Hiroshi Fukuda
Kato Kazuho
Hiroshi Fukuda