Title:
PROCESSING UNIT, SYSTEM AND METHOD TO BE FREELY DYNAMICALLY RESET
Document Type and Number:
Japanese Patent JP3785218
Kind Code:
B2
Abstract:
PURPOSE: To provide a processing unit or system equipped with a calculation environment to be dynamically reset for executing a program instruction for data processing.
CONSTITUTION: A system 10 of the calculation environment to be scalably, parallelly and dynamically reset is composed of a pair of S machines 12, T machines 14 corresponding to the respective S machines 12, general-purpose mutual connection matrix 16, a pair of I/O T machines 18, a pair of I/O devices 20 and master time base unit 22. Each S machine 12 is a computer, which can be freely dynamically reset, provided with a memory, first local time unit and processing unit to be freely dynamically reset. The processing unit is mounted by using a reprogrammable logic device set as an instruction fetch unit, data arithmetic unit and address arithmetic unit and these respective components are selectively reconstituted during program execution corresponding to the selection of a resetting interruption or a resetting instruction embedded in a pair of program instructions.
Inventors:
Michael baxter
Application Number:
JP9569096A
Publication Date:
June 14, 2006
Filing Date:
April 17, 1996
Export Citation:
Assignee:
株式会社リコー
International Classes:
G06F9/24; G06F9/30; G06F15/80; G06F9/312; G06F9/318; G06F9/38; G06F9/445; G06F9/45; G06F12/00; G06F15/173; G06F15/78; (IPC1-7): G06F9/24
Domestic Patent References:
| JP1125123A |
Attorney, Agent or Firm:
Hiroaki Sakai