Title:
プロセッサのアドレス発生ユニット
Document Type and Number:
Japanese Patent JP4624098
Kind Code:
B2
Abstract:
A processor includes a memory port for accessing a physical memory under control of an address. A processing unit executing instructions stored in the memory and/or operates on data stored in the memory. An address generation unit ("AGU") generates address for controlling access to the memory; the AGU being associated with a plurality of N registers enabling the AGU to generate the address under control of an address generation mechanism. A memory unit is operative to save/load k of the N registers, where 2<=k<=N, triggered by one operation. To this end, the memory unit includes a concatenator for concatenating the k registers to one memory word to be written to the memory through the memory port and a splitter for separating a word read from the memory through the memory port into the k registers.
Inventors:
Cornelis, Ha. Fan, Berkel
Patrick, PA A. Mübissen
Patrick, PA A. Mübissen
Application Number:
JP2004507987A
Publication Date:
February 02, 2011
Filing Date:
May 07, 2003
Export Citation:
Assignee:
NXP B.V.
International Classes:
G06F9/38; G06F12/00; G06F9/30; G06F9/312; G06F9/34; G06F9/42; G06F9/48; G06F12/02; G06F12/04; G06F12/06; G06F15/78; G06T1/60
Domestic Patent References:
| JP11154089A | ||||
| JP2001516916A |
Attorney, Agent or Firm:
Kenji Yoshitake
Hidetoshi Tachibana
Takeshi Sekine
Takahashi
Hidetoshi Tachibana
Takeshi Sekine
Takahashi