Title:
PROCESSOR STOP/TRAVELING CONTROL SYSTEM
Document Type and Number:
Japanese Patent JPH05344550
Kind Code:
A
Abstract:
PURPOSE: To control the stop/traveling of a processor through a loop bus by connecting the bus to respective processors, using one of the processors as a master and controlling the whole system including other processors through the bus.
CONSTITUTION: A CTLa 21 outputs a stop/traveling command for its corresponding processor to the loop bus 1 through a BIF 11 based upon a command outputted from a DIR 41 and a CTLb 22 reads out the stop/traveling command for the corresponding processor which is outputted from the bus 1 through a BIF 12. The processor CPs 32 is informed of the processor stop/traveling command by non-maskable interruption to control the stop/traveling of the processor CPs 32.
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Inventors:
SUETAKE AKIO
Application Number:
JP14513992A
Publication Date:
December 24, 1993
Filing Date:
June 05, 1992
Export Citation:
Assignee:
NEC CORP
International Classes:
G06F15/177; G06F15/16; H04Q3/545; (IPC1-7): H04Q3/545; G06F15/16
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)