Title:
PROCESSOR AND ERROR DETECTION METHOD
Document Type and Number:
Japanese Patent JP2021144426
Kind Code:
A
Abstract:
To provide a processor and an error detection method configured to detect an error generated in the processor more appropriately with a simple configuration.SOLUTION: A processor includes a pipeline control circuit which performs processing in accordance with an input instruction, and an ECC circuit which detects an error on the pipeline control circuit. The ECC circuit selects whether or not to execute error detection on the pipeline control circuit in accordance with the processing executed by the pipeline control circuit. Whether or not the ECC circuit executes error detection is defined for each instruction code which indicates processing to be executed by the pipeline control circuit.SELECTED DRAWING: Figure 3
Inventors:
CHIN YASUSHI
Application Number:
JP2020042171A
Publication Date:
September 24, 2021
Filing Date:
March 11, 2020
Export Citation:
Assignee:
NSITEXE INC
DENSO CORP
DENSO CORP
International Classes:
G06F9/38; G06F9/30; G06F11/10
Attorney, Agent or Firm:
Mamoru Suzuki
Shinji Kato
Takayuki Ishimoto
Shinji Kato
Takayuki Ishimoto