Title:
PROCESSOR INCORPORATING SYSTEM FOR MULTI-PROCESSOR SYSTEM
Document Type and Number:
Japanese Patent JPS6398762
Kind Code:
A
Abstract:
PURPOSE:To decrease the hardware quantity by performing communication between processors via a host during a processor incorporating mode and incorporating the processor despite noises caused by the unstable state of a power supply with omission of a constitution that detect a fixed state of the power supply. CONSTITUTION:The inter-processor communication is usually carried out via a communication line 40. When it is needed to incorporate a processor 30a, the communication switching parts 32b and 32c of processors 30b and 30c switch the inter-processor communication requests produced internally so that these requests are given to the host communication parts 31b and 31c. When the communication is carried out between the processors 30b and 30c, the part 31b informs a host 10 that the inter-processor communication information is held via a control part 20 and transmits the communication information to the host 10. This transferred communication information is sent to the processor 30c from an information transfer part 13 via the part 20.
Inventors:
TAJIMA MASAHIRO
Application Number:
JP24585186A
Publication Date:
April 30, 1988
Filing Date:
October 15, 1986
Export Citation:
Assignee:
NEC CORP
International Classes:
G06F15/16; G06F15/17; G06F15/177; (IPC1-7): G06F15/16
Attorney, Agent or Firm:
Uchihara Shin