Title:
プロセッサ及び情報処理装置
Document Type and Number:
Japanese Patent JP7010129
Kind Code:
B2
Abstract:
A processor includes: a plurality of processor cores; an interconnector including a reduction operation device and configured to communicate with another processor; a memory controller configured to control a main memory; a bus configured to couple the plurality of processor cores, the interconnector, and the memory controller to each other; and a reduction operation buffer coupled to the bus and the interconnector, wherein each of the processor cores writes control information to control the reduction operation device included in the interconnector and a value to be operated by the reduction operation device in the reduction operation buffer, and the interconnector reads out the control information and the value from the reduction operation buffer and delivers the control information and the value to the reduction operation device.
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Inventors:
Yuichiro Yasushima
Shinya Hiramoto
Yuji Kondo
Shinya Hiramoto
Yuji Kondo
Application Number:
JP2018080846A
Publication Date:
January 26, 2022
Filing Date:
April 19, 2018
Export Citation:
Assignee:
富士通株式会社
International Classes:
G06F9/38; G06F9/52; G06F15/173
Domestic Patent References:
| JP2012128808A |
Attorney, Agent or Firm:
Sakai International Patent Office