To reduce a hardware scale with respect to a configuration relating to processing of an interrupt request.

A processor includes: a plurality of hardware threads; a thread scheduler; a selection unit which selects an interrupt request to which a hardware thread as an instruction execution object is assigned, from among a plurality of interrupt requests to each of which one of the plurality of hardware threads is assigned to; and a determination unit which determines whether or not an interrupt is permitted in the hardware thread as the instruction execution object in response to the selected interrupt request.