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Title:
PROCESSOR WITH VERIFYING MEANS
Document Type and Number:
Japanese Patent JPH0342731
Kind Code:
A
Abstract:

PURPOSE: To obtain an accurate processing result by comparing outputs again after prescribed time lapses when the outputs are in discordance.

CONSTITUTION: Two ALU 1 and 2 execute the same arithmetic operation by a controller 3 by using the same input value set in the input value registers of arithmetic logic units (ALU) 1 and 2. Then, the outputs of two ALUs 1 and 2 are set in output value registers when the operation is completed, and respective values are compared in a comparing device 4. When they are in discordance, a discrimination device 5 holds the controller 4 and a subsequent operation is stopped. Then, the outputs of two ALUs 1 and 2 are compared after prescribed time elapses. Consequently, the control means of ALUs 1 and 2 is held for prescribed time when the two operation results are in discordance, the operation results are compared, and it is discriminated whether discordance occurs owing to delay in ALUs 1 and 2 or not.


Inventors:
KOSAKA KAZUKI
Application Number:
JP17865289A
Publication Date:
February 22, 1991
Filing Date:
July 11, 1989
Export Citation:
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Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
G06F11/18; (IPC1-7): G06F11/18
Attorney, Agent or Firm:
Masuo Oiwa (2 outside)



 
Next Patent: JPH0342732