To execute a product sum operation at a high speed with less hardware amount.

Analog voltages Xi respectively corresponding to the respective elements of a first input data string are inputted through input terminals 11-1n to capacitance switching circuits 101-10n. The digital control signals Ai of (m) bits corresponding to the respective elements of a second input string are inputted to the respective capacitance switching circuits 10i and the respective bits aj of the control signals Ai are respectively inputted to corresponding multiplexer circuits 6ij. In the multiplexer circuits 6ij, corresponding capacitance Cij is connected to the input terminal 1i or a reference potential VSTD corresponding to the values of the respective bits aj of the control signals Ai and voltages corresponding to the product of the respectively inputted analog voltages Xi and the control signals Ai are outputted from the respective capacitance switching circuits 10i. The output voltages of the respective capacitance switching circuits 10i are parallelly inputted to an operational amplifier 3 connected to a feedback capacitance Cf and the sum of the input voltages is outputted from the operational amplifier 3.