積和演算装置、積和演算回路、積和演算システム、及び積和演算方法

Japanese Patent JP7283477

B2

This multiply-accumulate operation device executes a multiply-accumulate operation with an analog circuit, and includes: a plurality of input lines; a plurality of multiplication units; an accumulation unit; a charging unit; and an output unit. Pulse signals having pulse widths corresponding to input values are input to the plurality of input lines. The plurality of multiplication units generates, on the basis of the pulse signals input to each of the plurality of input lines, charges corresponding to multiplication values obtained by multiplying the input values by weight values. The accumulation unit accumulates a sum of the charges corresponding to the multiplication values generated by each of the plurality of multiplication units. The charging unit charges, at a charging speed associated with an accumulation state of the accumulation unit, the accumulation unit in which the sum of the charges corresponding to the multiplication values have been accumulated. The output unit outputs a multiply-accumulate signal representing a sum of the multiplication values by executing threshold determination using a threshold value associated with the accumulation state of the accumulation unit on a voltage held by the accumulation unit after the charging by the charging unit is started.

Takashi Morie
Masatoshi Yamaguchi
Takeki Iwamoto
Right of Tamukai

JP2020530140A

May 30, 2023

July 04, 2019

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Sony Group Corporation

G06G7/60; G06G7/16; G06G7/184; G06N3/063

JP7141313A
JP2010061428A
JP2015195011A

Patent Attorney Corporation Minami Aoyama International Patent Office
Junichi Ohmori
Mitsuru Takahashi
Teppei Nakamura
Akira Orii
Masayoshi Sekine
Ayako Kaneko
Shintaro Kanayama
Ayako Chiba
Tomohisa Shiraka

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