Title:
PRODUCT
Document Type and Number:
Japanese Patent JPH08236780
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To minimize layout of a multi-gate structure, by arranging a charge carrier source and a destination, so that the conductivity of a 1st line between a 1st and a 2nd coupling points is controlled by a gate signal transmitted to a channel region by a 2nd line. SOLUTION: A line 70 is extended between a 1st and a 2nd coupling points and is coupled electrically with another element at the 1st and the 2nd coupling points. The line 70 is in the layer of a circuit containing a semiconductor material. A line 72 is the layer of another circuit and coupled so as to receive the gate signal. The line 72 crosses the line 70 in channels 80 and 82 and those lines contain 90 deg., so the lines form an L shape between the channels. On the line 70, the charge carrier source and destination are arranged, and then the gate signal transmitted by the line 71 to the respective channels controls the conductivity of the line 70 between the 1st and 2nd coupling points.
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Inventors:
II UEI UU
Application Number:
JP34299895A
Publication Date:
September 13, 1996
Filing Date:
December 28, 1995
Export Citation:
Assignee:
XEROX CORP
International Classes:
H01L21/768; H01L21/822; H01L23/482; H01L23/532; H01L23/522; H01L23/538; H01L27/04; H01L29/786; G02F1/1368; (IPC1-7): H01L29/786; H01L21/768; H01L27/04; H01L21/822
Attorney, Agent or Firm:
Masashi Kobori (1 person outside)
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