Title:
PRODUCTION OF MOS TYPE SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPS5455388
Kind Code:
A
Abstract:
PURPOSE:To produce a Si gate MOSIC of a small occupying area and high speed operation without high temperature heat treatment. CONSTITUTION:Openings 18 are made in the oxide thin film 17 formed on a P type Si substrate 11, and n type poly-Si 20 is laminated thereon and is heat treated to create n layers 21, 22. The layer 20 is selectively opened with holes, leaving poly-Si films 23 thru 25. Phosphorus ions are then implanted to make n layers 27, 28. Next, Si3N4 29, SiO2 30 are formed by CVD. Since the growth is performed at about 450 deg.C, the phosphorus of the layers 27, 28 does not migrate. Next, the film 30 is selectively etched by HF+NH2F and the film 29 by hot phosphoric acid. When Al wirings 31, 32 are made, the SiO2 film is etched even if the holes over the wiring 31 and gate 25 deviate, thus shorting does not occur. In this way, there is no high temperature treatment, the diffusion in the lateral direction of the source, drain is less and is suppressed, hence, higher speed of the element may be achieved and the variations in threshold value and the decrease in dielectric strength may be prevented.
Inventors:
KUNINOBU SHIGEROU
UENO ATSUSHI
ISHIHARA TAKESHI
UENO ATSUSHI
ISHIHARA TAKESHI
Application Number:
JP12265977A
Publication Date:
May 02, 1979
Filing Date:
October 12, 1977
Export Citation:
Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
H01L29/78; H01L21/3213; (IPC1-7): H01L21/90; H01L29/78
Domestic Patent References:
| JPS50137086A | 1975-10-30 | |||
| JPS50120584A | 1975-09-20 |
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