Title:
PRODUCTION OF MULTILAYER WIRING BOARD
Document Type and Number:
Japanese Patent JP3738071
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To increase the production yield of multilayer wiring board being employed as the board for hybrid IC.
SOLUTION: A second metal layer 15 is coated with a mask material PR corresponding to a specified circuit pattern and first and second metal layers 14, 15 are etched simultaneously thus forming first and second conductive paths 14A, 15A of lower layer simultaneously. Subsequently, under a state where the etchant remains stationary, overhang is removed at least from the surface of lower layer board by etching the second conductive path 15A of lower layer. Finally, upper layer conductive paths 23, 24 corresponding to a specified circuit pattern is formed thereon and an upper layer board 26 is bonded onto a lower layer board 10.
Inventors:
Yusuke Igarashi
Application Number:
JP34341395A
Publication Date:
January 25, 2006
Filing Date:
December 28, 1995
Export Citation:
Assignee:
Sanyo Electric Co., Ltd.
International Classes:
H05K3/06; H05K3/46; (IPC1-7): H05K3/46; H05K3/06
Domestic Patent References:
| JP7147476A | ||||
| JP7249872A | ||||
| JP6268372A | ||||
| JP61207069U | ||||
| JP5347482A |
Attorney, Agent or Firm:
Masamasa Shibano