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Title:
PROGRAM CIRCUIT DEVICE OF REDUNDANT CIRCUIT
Document Type and Number:
Japanese Patent JPS59113595
Kind Code:
A
Abstract:

PURPOSE: To make it unnecessary to impress a high voltage conventionally and design a circuit with a single power source by using the latch-up phenomenon of complementary transistors (TRs) as a means which fuses a fuse.

CONSTITUTION: When a negative surge voltage is impressed to an input terminal 16, an npn TR32 is turned on, and a current is flowed from an output terminal 22 toward the input terminal through a base resistance 31 of a pnp TR30, and the pnp TR30 is turned on. Therefore, a current is flowed from an output terminal 22 toward an earth point 21 through a base resistance 34 of an npn TR33, and the npn TR33 is turned on, and the pnp TR30 and the npn TR33 are kept turned-on, and what is called the latch-up phenomenon where a large current is flowed from the output terminal 22 toward the earth point 21 is generated. Consequently, this large current is flowed to a fuse 19 to fuse it, and the output terminal 22 obtains an "L" level, and the mode driving a redundant memory.


Inventors:
TOYOMOTO HIDEHARU
Application Number:
JP22566282A
Publication Date:
June 30, 1984
Filing Date:
December 20, 1982
Export Citation:
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Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
G11C17/00; G11C17/06; G11C29/00; G11C29/04; (IPC1-7): G11C29/00
Attorney, Agent or Firm:
Shinichi Kusano



 
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