PURPOSE: To perform normal operation by providing a delay control signal generation part, and performing control processing on the basis of the recognized delay time from the signal generation part when information transfer to an instruction register is delayed.

CONSTITUTION: A storage address register set timing from a control signal generation part 4 is held in a storage address register 2 through a control signal switching part 35, and a control storage device 1 sends out instructions. At this time, if a readout of the instruction information from the device 1 is delayed and incorrect information is held in an instruction register 6, improper operation is detected by a parity error detecting circuit 12. The switching part 35 is informed that the improper operation is detected, thereby reporting that to an external device. In response to an external restart instruction, the switching part 35 is controlled by various timing signals of recognized delay time from a delay control signal generation part 30 to reset the operation of the register 2, device 1, register 6, etc., to normal conditions.