PURPOSE: To provide an inexpensive program counter capable of simplifying a circuit configuration and improving the operational speed by reducing the number of transmission gates.

CONSTITUTION: First and second transmission gates 1 and 2 are connected through a first inverter means 4, and the output of the second transmission gate is connected to the Q output and the Q bar output through a second inverter means 5. The Q bar output is connected to the input of the first transmission gate 1 and the output of a third transmission gate having the data input is connected between the first transmission gate 1 and the first inverter means 4. The output of a NAND gate circuit 7 which takes the external clock signal CLK and a load signal LD as a clock signal to be supplied to the first and the second transmission gates 1 and 2 is used.