PURPOSE: To attain the detection of failure of a more strict program, by checking that a monitor timer reset instruction from a program enters the range for a prescribed count time.

CONSTITUTION: A monitor clock producing circuit 33 generates a timing pulse, which is inputted to a clock device counting a counter of a monitor timer 32. A carry output signal 385 of the counter is made active after a prescribed time if no reset input is given to the timer 32, a failure detection FF37 is set and a program failure detection signal line 40 is made active. When the program is operated normally, a monitor timer reset instruction is outputted via a processor bus 20. An I/O decoder 31 receives this instruction and outputs a timer reset signal 381. The monitor timer is reset by this signal.