PROGRAM RESTARTING CIRCUIT - NIPPON ELECTRIC CO

Title:

PROGRAM RESTARTING CIRCUIT

Document Type and Number:

Japanese Patent JPS59205648

Kind Code:

A

Abstract:

PURPOSE: To use the same memory address space in common by plural memories by controlling these memories with the reset FF output.

CONSTITUTION: When a switch SW1 is pushed, a processor 1 is reset. At the same time, a reset FF (RSFF)5 is set. Therefore the terminal E of an ROM6 and the terminal E of an RAM7 are set at L and H levels respectively. In other words, the ROM6 can be actuated. The processor 1 executes a program P6 of the ROM6, and this execution jumps to a program P8 immediately before the execution is ended with the program P6. In addition, an instruction which resets the RSFF5 is written to the first part of the program P8. Therefore the outputs Q and Q' are set at L and H levels respectively, and the operation of the ROM6 is inhibited, an the RAM7 can be operated. As a result, the processor 1 constantly uses both programs P7 and P8.

Inventors:

ITOU HIROSHI

Application Number:

JP7914983A

Publication Date:

November 21, 1984

Filing Date:

May 06, 1983

Export Citation:

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Assignee:

NIPPON ELECTRIC CO

International Classes:

G06F9/06; G06F12/06; G06F13/00; (IPC1-7): G06F9/06; G06F13/00

Attorney, Agent or Firm:

Sugano Naka

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