Title:
PROGRAMMABLE CONTROLLER
Document Type and Number:
Japanese Patent JPS61128302
Kind Code:
A
Abstract:
PURPOSE:To prevent a programmable controller from careless system down by dividing input data into plural groups to execute DMA transfer of the data groups and adding a bus checking pattern to each transfer group to inspect the pattern on the slave CPU side. CONSTITUTION:A main CPU1a writes the input data of an I/O memory 4 in an input area of an I/O memory 3a, and then while referring an I/O data area of the memory 3a, executes a user instruction stored in a user program memory 2a. Then, the CPU1a rewrites the output data of the memory 3a on the basis of the executed result and transfers output data stored in an output data area of the memory 3a to an output terminal of an I/O device 4. In addition to the normal operation, the CPU1a executes the DMA transfer of the data of the memory 3a to an input area of a memory 3b on the CPU1b side through a DMA controller 5 at the end of a series of cycles. Consequently, common I/O data are always coincident, and if the CPU1a is downed, the control right is transferred to the CPU1b.
Inventors:
TOYAMA HISAO
Application Number:
JP25070884A
Publication Date:
June 16, 1986
Filing Date:
November 28, 1984
Export Citation:
Assignee:
OMRON TATEISI ELECTRONICS CO
International Classes:
G05B9/03; G05B19/05; (IPC1-7): G05B9/03
Domestic Patent References:
| JPS5510614A | 1980-01-25 | |||
| JPS5750039A | 1982-03-24 | |||
| JPS53114632A | 1978-10-06 |
Attorney, Agent or Firm:
Shigenori Wada