Title:
PROGRAMMABLE CONTROLLER
Document Type and Number:
Japanese Patent JPS6474602
Kind Code:
A
Abstract:
PURPOSE:To perform the quick processing by executing the comparison processing of the counted result of a pulse signal by hardware and taking the execution result into a CPU part through a three-state buffer. CONSTITUTION:A CPU part 3 issues a step-up signal to step up the count value given from a program 13 to a user memory 4. In case of a two-word instruction, the step-up signal is issued again by the CPU part 3 to store the second word in a memory 4 in a latch 19. Stored contents of the latch 19 are transmitted to the B side of a comparator 18. Meanwhile, the pulse signal from an encoder 9 is counted by a counter 12, and its contents are given to the A side of the comparator 18. The comparator compares the input A with the input B and transmits the output signal of the comparison result to three-state buffers 21a, 21b, and 21c. One of buffers 21a, 21b, and 21c is selected by the output of an address decoder 20, and the result of the comparator 18 is read out to the CPU part 3.
Inventors:
KUROKAWA NAOHIRO
Application Number:
JP22990587A
Publication Date:
March 20, 1989
Filing Date:
September 16, 1987
Export Citation:
Assignee:
HITACHI LTD
International Classes:
G05B19/05; G05B19/04; (IPC1-7): G05B19/04