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Title:
PROGRAMMABLE COUNTER CIRCUIT
Document Type and Number:
Japanese Patent JPS62122324
Kind Code:
A
Abstract:

PURPOSE: To obtain reset function of the titled circuit by providing a function equivalent to a reset function without the special provision of reset function externally so as to decode a signal of a program input terminal thereby using a signal of a decoder output.

CONSTITUTION: A program counter 1 has n-set of program inputs 2 for setting the frequency division, a clock input terminal 3, a reset terminal 4, and a frequency division output 5, and the n-set of program inputs 2 are connected respectively to n-input of decoder circuit 6. An output of the decoder circuit 6 is connected to the reset terminal 4 of the programmable counter 1. When a signal for setting frequency division is fed to the n-set of program input terminals 2 and a signal of reset release is fed to the reset terminal of the program counter 1 from the decode circuit 6, the clock pulse inputted from the clock input terminal 3 is outputted from the frequency division output terminal 5 in response to the frequency division set by the program.


Inventors:
URIYA SUSUMU
KIMURA KATSUHARU
ASHIDA SHIGEAKI
MINAMI YOICHIRO
Application Number:
JP26280385A
Publication Date:
June 03, 1987
Filing Date:
November 21, 1985
Export Citation:
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Assignee:
NEC CORP
International Classes:
H03K23/66; (IPC1-7): H03K23/66
Attorney, Agent or Firm:
Uchihara Shin



 
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