Title:
PROGRAMMABLE FREQUENCY DIVIDER CIRCUIT
Document Type and Number:
Japanese Patent JPH05191273
Kind Code:
A
Abstract:
PURPOSE: To eliminate restriction on a range of value of a divisor to be used depending on the number of cells. CONSTITUTION: The circuit is provided with a prescaler consisting of (p) pieces of cascade connection frequency divider cells and the cell of an order (i) of the cascade connection frequency divider cell is set to be programmable to set an ordinary divisor as 2 and to simultaneously divide input frequency supplied to the cell to one third. A signal named as a gating signal and to correct duration width and a position with operating frequency of the cell (i) is supplied as the signal to enable a mode programmed to the following cell of the order i-1. The prescaler PPSC is related to a counting means CNT so that a programmable divisor R which is equivalent to M.2
+N is generated. In this case, M is an integer to be applied to the counting means CNT, (p) is number of cells of the prescaler PPSC and N is the integer to be applied to a programming input terminal of the prescaler PPSC.
Inventors:
FUIRITSUPU GORISU
Application Number:
JP14572292A
Publication Date:
July 30, 1993
Filing Date:
June 05, 1992
Export Citation:
Assignee:
PHILIPS NV
International Classes:
H03K23/66; H03K23/64; (IPC1-7): H03K23/64
Attorney, Agent or Firm:
Akihide Sugimura (5 outside)