Title:
PROGRAMMABLE FREQUENCY DIVIDER, PLL SYNTHESIZER AND RADAR APPARATUS
Document Type and Number:
Japanese Patent JP2017228894
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To provide a programmable frequency divider, a PLL synthesizer and a radar apparatus capable of achieving stable operation independently of temperature variation, voltage variation, process variation, and so on.SOLUTION: A pulse swallow type programmable frequency divider 5 includes a modulus frequency divider 51, a pulse counter 52 for counting an output signal fout from the modulus frequency divider and outputting frequency-divided signals Fo, RST, and a swallow counter 53 for counting the output signal from the modulus frequency divider and resetting the count value on the basis of the frequency-divided signals from the pulse counter to control the modulus frequency divider on the basis of an output signal DMP from the swallow counter, and includes also a control signal delay circuit 54 connected between an output terminal 53o of the swallow counter and a control terminal 51c of the modulus frequency divider to delay the output signal from the swallow counter and generate a control signal DMP' for controlling the modulus frequency divider.SELECTED DRAWING: Figure 7
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Inventors:
MATSUMURA HIROSHI
Application Number:
JP2016122828A
Publication Date:
December 28, 2017
Filing Date:
June 21, 2016
Export Citation:
Assignee:
FUJITSU LTD
International Classes:
H03K23/64; H03L7/18
Attorney, Agent or Firm:
Atsushi Aoki
Koichi Itsubo
Tsutomu Kono
Tetsuo Miyamoto
Koichi Itsubo
Tsutomu Kono
Tetsuo Miyamoto