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Title:
PROGRAMMABLE FREQUENCY DIVIDER
Document Type and Number:
Japanese Patent JPH0590951
Kind Code:
A
Abstract:

PURPOSE: To select a frequency divided output of a small width in the unit of an original clock without remarkable increase in the circuit scale when a desired frequency division ratio is limited to a certain range.

CONSTITUTION: An original clock pulse is counted and a frequency divider 12 able to select at least two kinds of different frequency division ratio counts the original clock pulse and a frequency divided output is fed to an interruptible input terminal of a control section 13. The control section 13 implements prescribed interrupt processing in the presence of an interrupt input and implements programmable frequency division processing for each interrupt processing and applies selection control of the frequency division ratio of the frequency divider 12 for each cyclic period of the programmable frequency division processing.


Inventors:
ITO KENJI
Application Number:
JP13935791A
Publication Date:
April 09, 1993
Filing Date:
June 12, 1991
Export Citation:
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Assignee:
TOSHIBA CORP
International Classes:
H03K21/00; H03K23/64; (IPC1-7): H03K21/00; H03K23/64
Attorney, Agent or Firm:
Takehiko Suzue



 
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