PROGRAMMABLE LOGIC ARRAY

Title:

PROGRAMMABLE LOGIC ARRAY

Document Type and Number:

Japanese Patent JPH01238219

Kind Code:

A

Abstract:

PURPOSE: To rewrite the program of a programmable logic array by controlling information for connecting an addition transistor or not by information written in a static cell.

CONSTITUTION: For instance, when a word line is externally selected in a RAM cell for storing '1', '0' information, transmission gates TR0, TR1 are turned on and prescribed information is written in inverter latches R0, R1 in the AND plane element of a PLA through a bit line BL, the inverse of BL. When the potential of the A point of the input side of the latches R0, R1 is '1', the output of the A point of an output side is defined to be '0' and accordingly, the connection of the addition transistor ANO and a product term line is separated. When the potential of the 3 point is '0..., they are connected. Accordingly, the prescribed information can be written to the PLA element.

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Inventors:

MIURA DAISUKE

Application Number:

JP6362388A

Publication Date:

September 22, 1989

Filing Date:

March 18, 1988

Export Citation:

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Assignee:

FUJITSU LTD

International Classes:

G06F7/00; H03K19/177; (IPC1-7): G06F7/00; H03K19/177

Attorney, Agent or Firm:

Aoki Akira (3 outside)

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