Title:
PROGRAMMABLE LOGIC CIRCUIT PROVIDED WITH REDUNDANT CIRCUIT
Document Type and Number:
Japanese Patent JP2003188712
Kind Code:
A
Abstract:
To provide a routing architecture independent of horizontal and vertical wires over most parts of a device.
The programmable logic circuit is provided with a plurality of signal paths each spread over a plurality of logic region rows and provided with a plurality of lines, a normal mode stitching circuit for coupling the first lines of a plurality of signal paths to the second lines of a plurality of signal paths and a redundant mode stitching circuit for coupling the tails of the first lines of a plurality of signal paths to the second lines of a plurality of signal paths.
Inventors:
CHRISTOPHER LANE
ZAVERI KETAN
YI HYUN
POWELL GILES
LEVENTIS PAUL
JEFFERSON DAVID
LEWIS DAVID
NGUYEN TRIET
SANTURKAR VIKRAM
CHAN MICHAEL
LEE ANDY
BRIAN JOHNSON
CASHMAN DAVID
ZAVERI KETAN
YI HYUN
POWELL GILES
LEVENTIS PAUL
JEFFERSON DAVID
LEWIS DAVID
NGUYEN TRIET
SANTURKAR VIKRAM
CHAN MICHAEL
LEE ANDY
BRIAN JOHNSON
CASHMAN DAVID
Application Number:
JP2002301079A
Publication Date:
July 04, 2003
Filing Date:
October 15, 2002
Export Citation:
Assignee:
ALTERA CORP
International Classes:
H01L21/82; H03K19/177; (IPC1-7): H03K19/177; H01L21/82
Attorney, Agent or Firm:
Shusaku Yamamoto (2 outside)
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