Title:
PROGRAMMABLE LOGIC CONTROLLER
Document Type and Number:
Japanese Patent JPS57174705
Kind Code:
A
Abstract:
PURPOSE:To eliminate the logical conflict of a program in the output simulation mode with a simple constitution, by rewriting the designated output data of an input/output memory with a forcible operation input and then inhibiting the rewriting as an output data for execution of an instructuion. CONSTITUTION:A program console 8 supplies with a forcible operation an input/ output address for forcible operation and the set or reset data to the input/output address. Receiving the forcible operation input, an access is given to an input/output memory 7 after the working cycle of a control circuit 6C functioning as an input/output replacing means and before the working cycle of an arithmetic control circuit 5 functioning as an instruction executing means. Then the supplied set or reset data is forcibly written into the supplied input/output address. The data rewriting is inhibited 17 concerning the input/output address which is forcibly supplied at the memory 7 when the circuit 5 is working in a certain period of the forcible operation input. As a result, the input/output simulation is facilitated to eliminate the logical conflict of a program in the output simulation mode.
Inventors:
KATOU YUKIO
Application Number:
JP5960081A
Publication Date:
October 27, 1982
Filing Date:
April 20, 1981
Export Citation:
Assignee:
OMRON TATEISI ELECTRONICS CO
International Classes:
G05B19/05; (IPC1-7): G05B19/02
Domestic Patent References:
| JPS53117182A | 1978-10-13 |