Title:
マルチプライヤを含んだプログラマブルロジックデバイスならびにそのリソース使用を低減するための構成
Document Type and Number:
Japanese Patent JP4291829
Kind Code:
B2
Abstract:
In a programmable logic device having dedicated multiplier circuitry, some of the scan chain registers normally used for testing the device are located adjacent input registers of the multipliers. Those scan chain registers are ANDed with the input registers, and can be loaded with templates of ones and zeroes. This allows, e.g., subset multiplication if the least significant bits are loaded with zeroes and the remaining bits are loaded with ones. The multipliers preferably are arranged in blocks with other components, such as adders, that allow them to be configured as finite impulse response (FIR) filters.
In such configurations, the scan chain registers can be used to load filter coefficients, avoiding the use of scarce logic and routing resources of the device.
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Inventors:
Martin langhammer
Chao Kai Wan
Gregory Star
Chao Kai Wan
Gregory Star
Application Number:
JP2006130820A
Publication Date:
July 08, 2009
Filing Date:
May 09, 2006
Export Citation:
Assignee:
Altera Corporation
International Classes:
G06F7/00; H03K19/177; G06F7/52; H01L21/82; H03H17/06
Domestic Patent References:
| JP200142010A | ||||
| JP2242425A | ||||
| JP287400A | ||||
| JP5674668A | ||||
| JP63182585A |
Attorney, Agent or Firm:
Hidesaku Yamamoto
Takaaki Yasumura
Natsuki Morishita
Takaaki Yasumura
Natsuki Morishita