Title:
PROGRAMMABLE LOGICAL ARRAY BY SOFTWARE
Document Type and Number:
Japanese Patent JPS61192125
Kind Code:
A
Abstract:
A software programmable logic array ("SPLA") is disclosed for creating a logic array which can be dynamically programmed to provide any combination of predetermined outputs from any combination of desired inputs. The foregoing is accomplished by providing a first plane 13 of programmable bits for producing a plurality of AND terms which are input to a second plane 17 of programmable bits for producing a plurality of OR terms, which are then input into a third plane 21 of programmable bits for producing a plurality of outputs, each having a desired polarity. In the AND plane each bit can be programmed to produce 0 (i.e. regardless of input), 1, input or inverse of input, prior to the ANDing. In the OR plane each bit can be programmed to produce 0 or input, prior to the ORing. In the third plane, each bit can be programmed to produce input or inverse of input.
Inventors:
MAAKU PORETSUTO
Application Number:
JP22662885A
Publication Date:
August 26, 1986
Filing Date:
October 11, 1985
Export Citation:
Assignee:
INTEL CORP
International Classes:
G06F17/50; H03K19/177; (IPC1-7): H03K19/177
Domestic Patent References:
| JPS59207743A | 1984-11-24 |
Attorney, Agent or Firm:
Masaki Yamakawa