Title:
PROGRAMMABLE LOGICAL DEVICE
Document Type and Number:
Japanese Patent JPH09261039
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To allow a user to easily program, so as to realize a desired logical function by providing a means connecting input and output leads to mutual connection lines by respective programming and a means mutually connecting the mutual connecting lines by programming. SOLUTION: Each CLE of nine CLEs 40-1 to 40-9 is provided with plural input leads and not less than one output lead. Each input lead is provided with plural access connection parts and each of them connects a selected general connection lead to an input lead. These logical elements 40-1 to 40-9 are arranged on an integrated circuit chip with a general mutual connection constituting body provided with a programmable access connection part and a programmable general mutual connection part for connecting a general mutual connection lead and various leads to another lead. Then an electrical path from the output lead of one CLE to the input lead of another CLE involves the general mutual connection part.
More Like This:
Inventors:
UIRIAMU ESU KAATAA
ROSU EICHI FURIIMAN
ROSU EICHI FURIIMAN
Application Number:
JP26212796A
Publication Date:
October 03, 1997
Filing Date:
October 02, 1996
Export Citation:
Assignee:
XILINX INC
International Classes:
H01L27/118; H03K19/0175; H03K19/173; H03K19/177; H01L21/82; H03K19/20; (IPC1-7): H03K19/173; H01L21/82; H03K19/177
Domestic Patent References:
| JPS59161839A | 1984-09-12 |
Attorney, Agent or Firm:
Kazuo Kobashi (1 person outside)