Title:
PROGRAMMABLE LOW-POWER HIGH-FREQUENCY DIVIDER
Document Type and Number:
Japanese Patent JP3935901
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a programmable low-power high-frequency divider circuit.
SOLUTION: A fast latch includes: a NAND stage adapted to receive a clock signal and a data input signal; a clocked inverter stage wherein a first input of the clocked inverter stage is coupled to the output of the NAND stage and a second input of the clocked inverter stage is coupled to the clock signal; a first inverter stage wherein a first input of the first inverter stage is coupled to an output of the clocked inverter and a second input of the first inverter stage is coupled to a reset signal; and a second inverter stage, having an output, wherein an input of the second inverter stage is coupled to an output of the first inverter stage. The fast latch is suitable for use in frequency divider circuits. A homologue of frequency dividers using the fast latch, a unique 3/4 divider and a 2 divider not using the fast latch are also disclosed.
Inventors:
John S Austin
Ram Kelkar
Pradep Tiagarajan
Ram Kelkar
Pradep Tiagarajan
Application Number:
JP2004258491A
Publication Date:
June 27, 2007
Filing Date:
September 06, 2004
Export Citation:
Assignee:
INTERNATIONAL BUSINESS MASCHINES CORPORATION
International Classes:
H03K23/64; H03K5/156; H03K21/00; H03K21/10; H03K21/38; H03K23/44; H03K23/66; (IPC1-7): H03K23/64
Domestic Patent References:
| JP6045915A | ||||
| JP8162946A | ||||
| JP5327484A | ||||
| JP7170173A | ||||
| JP9307430A | ||||
| JP2002043930A | ||||
| JP2003188719A | ||||
| JP11111940A | ||||
| JP2000181946A | ||||
| JP10111674A | ||||
| JP11154710A | ||||
| JP2000209082A | ||||
| JP61198817A | ||||
| JP2000509222A |
Foreign References:
| US5917355 |
Other References:
山本外史著,「精解演習 ディジタル回路」,日本,株式会社廣川書店,1974年 9月25日,207~210頁,ジョンソン・カウンタ
湯山俊夫著,「ディジタルIC回路の設計」,日本,CQ出版株式会社,1987年 1月10日,173頁~176頁、62頁~74頁,ジョンソン・カウンタ、エッジ検出回路又はワンショット・マルチバイブレータ
W.N.CARR他,「MOS/LSI Design and Application」,米国,McGRAW-HILL BOOK COMPANY,1972年,77頁、126頁,二入力NAND、CMOSインバータ
湯山俊夫著,「ディジタルIC回路の設計」,日本,CQ出版株式会社,1987年 1月10日,173頁~176頁、62頁~74頁,ジョンソン・カウンタ、エッジ検出回路又はワンショット・マルチバイブレータ
W.N.CARR他,「MOS/LSI Design and Application」,米国,McGRAW-HILL BOOK COMPANY,1972年,77頁、126頁,二入力NAND、CMOSインバータ
Attorney, Agent or Firm:
Hiroshi Sakaguchi
Yoshihiro City
Takeshi Ueno
Yoshihiro City
Takeshi Ueno
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