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Title:
PROGRAMMABLE REGISTER
Document Type and Number:
Japanese Patent JPS60245304
Kind Code:
A
Abstract:

PURPOSE: To adjust easily a resistance value by constituting a programmable register by connecting in parallel plural series circuits of an FET of normal-on, a resistance and a pre-arcing fuse.

CONSTITUTION: A programmable register is constituted by connecting in parallel plural series circuits of FETs Tr1∼Trn of normal-on, resistances R1∼Rn, and pre-arcing fuses f1∼fn. A voltage is applied to the gate of a transistor and it is turned off, and an optimum resistance value is detected by monitoring a resistance of between (a) and (b) by a computer. When an unnecessary resistance is determined, the transistor is turned off, and thereafter, a sufficient current by which a pre-arcing fuse fi is cut is made to flow between a terminal Ti and (b). In this way, write of a resistance value can be executed easily.


Inventors:
BABA YOSHIAKI
AKIYAMA TATSUO
TSURU KAZUO
ETSUNO YUTAKA
Application Number:
JP10201184A
Publication Date:
December 05, 1985
Filing Date:
May 21, 1984
Export Citation:
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Assignee:
TOSHIBA KK
International Classes:
H01C13/02; H03H7/24; H03H11/24; (IPC1-7): H01C13/02; H03H7/24
Attorney, Agent or Firm:
Takehiko Suzue



 
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