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Title:
PROM WRITER WRITING SYSTEM
Document Type and Number:
Japanese Patent JPS6047296
Kind Code:
A
Abstract:

PURPOSE: To improve the working efficiency by providing the 1st write and 2nd write sections writing data of an even number address and an odd number address of a write memory respectively to write the data of the even number address and the odd number address at the same time.

CONSTITUTION: A central control section 1 inputs a write data from a data input section 2 and stores the data to a write memory section 3. Then the data of the even and odd number addresses at a memory part 3 are transmitted respectively to a write circuit I 4 and a write circuit II5. The circuits I 4 and II5 write the data to the PROM of PROM loading sections I 6, II7 at the same time. Thus, in writing data in 16-bit unit by using two PROMs of 8-bit and a PROM writer having a memory in the unit of 8-bit, the even number address of the memory is corresponded to the low-order 8-bit and the odd number address is corresponded to the high-order 8-bit, and the data is written separately by the 1st and 2nd write sections respectively at the same time, then the job efficiency is improved.


Inventors:
TAZAKI YOSHIYUKI
Application Number:
JP15458483A
Publication Date:
March 14, 1985
Filing Date:
August 24, 1983
Export Citation:
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Assignee:
NIPPON ELECTRIC CO
International Classes:
G11C17/00; (IPC1-7): G11C17/00
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)



 
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