Title:
INPUT/OUTPUT PROTECTING CIRCUIT
Document Type and Number:
Japanese Patent JP3022690
Kind Code:
B2
Abstract:
PURPOSE: To eliminate the dependence on the chip size of the resistant voltage of an input/output protecting circuit by reducing an impedance between a power source and GND at the time of an excessive surge voltage being inputted to the input.
CONSTITUTION: An aluminum gate transistor TR 5 which has the gate, the source, and the drain connected to an input terminal A, a ground terminal VSS, and a power terminal VCC respectively is provided; and when an excessive surge voltage is inputted to the input terminal A, the aluminum gate TR 5 is turned on to reduce the impedance between the power terminal VCC and the ground terminal VSS, thus eliminating the dependence on the chip size of the withstand voltage of the input protecting circuit.
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Inventors:
Shigeru Maruyama
Application Number:
JP25857492A
Publication Date:
March 21, 2000
Filing Date:
September 28, 1992
Export Citation:
Assignee:
NEC IC Microcomputer System Co., Ltd.
International Classes:
H03K17/00; H03K17/08; (IPC1-7): H03K17/00; H03K17/08
Domestic Patent References:
| JP52127149A |
Attorney, Agent or Firm:
Naoki Kyomoto