Title:
PROTECTION CIRCUIT FOR CMOS INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPH09307426
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To provide a protection circuit with can prevent the latch-up of a CMOS circuit having plural voltage sources. SOLUTION: A protection circuit 50 of a CMOS integrated circuit that is biased by the 1st voltage VCC and the 2nd voltage VDD consists of a voltage divider, a voltage comparator 53 and a switch 55. The highest level of the voltage VCC is higher than that of the voltage VDD. The voltage divider divides the voltage VCC, and the comparator 53 compares the divided VCC with the voltage VDD. The on-off operations of the switch 55 are controlled by the comparator 53. If the divided VCC is lower than the VDD, the switch 55 cuts application of the divided VCC to the CMOS integrated circuit. Thereby, a forward bias current path is not formed in the CMOS integrated circuit even when both voltage VCC and VDD reach each highest level separately from each other.
Inventors:
YU DAIRITSU
YOU RIYOUGEN
YOU RIYOUGEN
Application Number:
JP24386796A
Publication Date:
November 28, 1997
Filing Date:
September 13, 1996
Export Citation:
Assignee:
KAHOU DENSHI KOFUN YUUGENKOUSH
International Classes:
H01L21/822; H01L21/8238; H01L27/02; H01L27/06; H01L27/092; H02H9/04; H01L27/04; H03K19/003; H03K19/0948; (IPC1-7): H03K19/0948; H01L27/04; H01L21/822; H01L27/06; H01L21/8238; H01L27/092
Attorney, Agent or Firm:
河野 登夫 （外１名）
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