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Title:
PROTECTION OF INTEGRATED CIRCUIT HAVING VOLTAGE VARIABLE MATERIAL
Document Type and Number:
Japanese Patent JP2000200869
Kind Code:
A
Abstract:

To protect a voltage variable integrated circuit against transient of EOS(electrical overstress) by providing a voltage variable material layer on an integrated circuit die while filling the gap between a plurality of I/0 pads and a conductive guard rail.

An integrated circuit is provided, on the surface of a die 10, with a plurality of conductive I/0 pads 25 connected electrically with a functional die area 20. A conductive guard rail 30 is provided contiguously to the I/0 pads 25 on the die 10 and a metal trace is provided. A gap 25a is formed between the guard rail 30 and each I/0 pad 25 and filled with a voltage variable material 35. According to the arrangement, the integrated circuit can be protected against extremely high energy associated with EOS transient.


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WO/2004/059734TESTABLE ELECTROSTATIC DISCHARGE PROTECTION CIRCUITS
JPH118305SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF
Inventors:
WHITNEY STEPHEN J
Application Number:
JP34871899A
Publication Date:
July 18, 2000
Filing Date:
December 08, 1999
Export Citation:
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Assignee:
LITTELFUSE INC
International Classes:
H01L23/58; H01C7/10; H01C7/12; H01L23/31; H01L23/62; (IPC1-7): H01L23/58
Domestic Patent References:
JPH02152204A1990-06-12
JPS6281050A1987-04-14
JPS5852866A1983-03-29
JPS63100702A1988-05-02
JPH05235274A1993-09-10
JPH08321586A1996-12-03
JPH09321220A1997-12-12
JPH10505462A1998-05-26
Foreign References:
US3327272A1967-06-20
Attorney, Agent or Firm:
Takashi Ishida (4 others)



 
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