Title:
PSEUDO HALFTONE BINARIZATION CIRCUIT
Document Type and Number:
Japanese Patent JPS6373771
Kind Code:
A
Abstract:
PURPOSE:To reproduce a pseudo halftone from which the influence of a fixed pattern noise is removed and to improve the picture quality of a reproduced picture by forming a halftone slice level by the use of a shading waveform at the time of being bright, the fixed pattern noise and a dither matrix. CONSTITUTION:The output (e) of a contact sensor 1 passes an analog signal processing circuit 2, a sample/hold circuit 3, digitally converted in an A/D converting part 5 and inputted to a shading writing control part 6. The shading writing control part 6 stores the shading waveform at the time of reading an all white original in a bright time shading waveform storage part 7 and stores the fixed pattern noise indicated by the shading waveform at the time of reading an all black original in a dark time shading waveform storage part 8. An arithmetic part 10 executes an operation of an expression (1) by using signals A, B taken out from the storage part 7, 8 respectively and a gradation level signal alphaij from a dither matrix pattern generating part 9, outputs the arithmetic result as the halftone slice level signal C and a binarization circuit 11 binarizes the output (h) of the circuit 3 by considering the signal C to be a threshold.
Inventors:
KOMATSU MASAYUKI
KOSEKI TAKASHI
WAKAYAMA KAZUKO
TSUJI HIROKUNI
KAWAMURA HIROSHI
KOSEKI TAKASHI
WAKAYAMA KAZUKO
TSUJI HIROKUNI
KAWAMURA HIROSHI
Application Number:
JP21699786A
Publication Date:
April 04, 1988
Filing Date:
September 17, 1986
Export Citation:
Assignee:
HITACHI LTD
International Classes:
H04N1/40; (IPC1-7): H04N1/40
Attorney, Agent or Firm:
Masami Akimoto