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Patent Searching and Data


Title:
PSEUDO PATTERN GENERATING/CONFIRMING CIRCUIT
Document Type and Number:
Japanese Patent JPH03188722
Kind Code:
A
Abstract:

PURPOSE: To reduce a circuit scale by using a pseudo pattern generating/ confirming circuit for simultaneous communication of plural channels to decrease the test time due to the preparation of test or the like, and transmitting the pattern among plural channels.

CONSTITUTION: In the case of applying communication test for transmission and reception between a terminal side equipment 11 and a transmission line side equipment 11, contacts of a 1st switch 13 and a 2nd switch 14 are connected to the position (b) to send a 1st cycle 511th pseudo pattern of 9-bit constitution at terminals D0-D8 of a 1st RAM 3 to the transmission line side equipment 11 via the 1st switch 13. A pseudo pattern confirming section 6 inputs the 1st cycle 511th pseudo pattern inputted via the 2nd switch 14 to a comparator 9 and a channel address of 5-bit constitution from a control memory 1 is inputted to the 2nd RAM 7 and compared with a read pseudo data and the result is sent. Similarly, the readout/write is repeated between the 2nd RAM 7 and a 2nd pseudo pattern generating circuit 8.


Inventors:
FUCHI YASUHIRO
Application Number:
JP32988989A
Publication Date:
August 16, 1991
Filing Date:
December 19, 1989
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
H04J3/14; H04L69/40; H04M3/26; (IPC1-7): H04J3/14; H04M3/26
Attorney, Agent or Firm:
Sadaichi Igita