PURPOSE: To obtain a random code of long period by providing memories corresponding to a delay element of a feedback shift register and a tap and reading out both memories round and counting the logical sum between both outputs and writing a binary of the least significant digit in the most significant digit position of the memory.

CONSTITUTION: A memory 1 corresponding the the delay element of a feedback shift register circuit and a memory 2 where the connection state of the feedback tap are provided. Contents of the memory 1 are successively shifted by one address to read out memories 1 and 2 round. Both outputs are inputted to an AND gate 7 to obtain the logical sum, and this value is counted by a counter 8, and code output '0' or '1' is obtained in case of an even or an odd. This code output is written in the most significant digit position of the memory to generate the pseudo-random code of long period.