To increase the randomness of pseudorandom numbers generated by a pseudorandom number generator.

The pseudorandom number generator 1 comprises pseudorandom number generation circuits 30-1 to 30-4 and a data generation circuit 20 connected to the first stage 30-1. Each pseudorandom number generation circuit comprises an input terminal for N-bit input data Din, an N-bit register, an output terminal for output data Dout from the N-bit register, and a modulation circuit on a feedback path from the output to input of the N-bit register. The modulation circuit modulates DRout from the N-bit register with Din to generate DRin to be input into the N-bit register. The data generation circuit 20 generates N-bit random number data Drnd from count values of a plurality of clock signals CLK1, CLK3 and CLK4, and outputs Drnd as Din to the first stage pseudorandom number generation circuit 30-1.

COPYRIGHT: (C)2010,JPO&INPIT