Title:
PSK SIGNAL ELIMINATING CIRCUIT FROM PSK VIDEO INFORMATION MULTIPLEX SIGNAL
Document Type and Number:
Japanese Patent JPS63256089
Kind Code:
A
Abstract:
PURPOSE:To eliminate only a DPSK signal in an excellent way by providing a BPF extracting the DPSK signal and an arithmetic circuit adding or subtracting the DPSK signal from the BPF to/from a multiplex signal between the DPSK signal and an FM color difference signal. CONSTITUTION:A delay time of the BPF 36 is a half the period (t) of the carrier wave of the DPSK signal. The arithmetic circuit 42 is an arithmetic circuit summing an output of an LPF 8 and an output of the BPF 36. The component of the DPSK signal in the output signal of the LPF 8 is shown in a figure (b). A signal retarded by a half period more than the signal shown in a figure (b) is outputted from the BPF 36 as shown in a figure (c). The component of the DPSK signal outputted from the arithmetic circuit 42 is shown in a figure (d). A noise N1 is produced in 2.44musec from the point of time of data switching, but the component of the DPSK signal is eliminated in an excellent way during the period other than the said period.
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Inventors:
YAMAMOTO TOMOJI
ONAKA TAKASHI
ONAKA TAKASHI
Application Number:
JP9016287A
Publication Date:
October 24, 1988
Filing Date:
April 13, 1987
Export Citation:
Assignee:
SANYO ELECTRIC CO
International Classes:
H04N9/79; G11B20/00; H04J4/00; H04L27/22; H04N9/86; (IPC1-7): G11B20/00; H04J4/00; H04L27/22; H04N9/79; H04N9/86
Attorney, Agent or Firm:
Takuji Nishino