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Title:
PULSE DURATION CONTROL CIRCUIT
Document Type and Number:
Japanese Patent JPS55121744
Kind Code:
A
Abstract:

PURPOSE: To realize two types of the overcurrent protective circuit systems simultaneously by securing the logic product between the output of the R/S flip-flop and the pulse duration control signal of the comparator, thus attaining the standardization of the control circuit of the switching regulator.

CONSTITUTION: The input signal is supplied to input terminals 66 and 67 of error amplifier 64, and the output is supplied to the inverse input terminal of comparator 63 in which the ramp waveform of ramp generator 62 synchronized with the clock pulse of clock pulse generator 61 is supplied to the non-inverse input terminal. NOR gates 72 and 73 function as the R/S flip-flop which uses the clock pulse and external terminal 69 for the set input and preset input each and then the output of NOR gate 73 for the Q output. The Q output is supplied to AND gate 65, and then the output signal to which the logic product is secured to the signal of comparator 63 is supplied to output terminal 70.


Inventors:
YAMASHITA HARUKI
Application Number:
JP2971179A
Publication Date:
September 19, 1980
Filing Date:
March 14, 1979
Export Citation:
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Assignee:
NIPPON ELECTRIC CO
International Classes:
H03K7/08; G01R29/027; G05F1/56; H03K17/08; (IPC1-7): G05F1/64; H03K7/08; H03K17/08



 
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