Title:
PULSE GENERATING CIRCUIT
Document Type and Number:
Japanese Patent JP2883059
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To form a pulse which has been subjected to pulse duration modula tion, using a single-integrated circuit by transmitting an address signal with a prescribed timing, based on a signal which has reversely-processed the address of a word read-out from a memory.
SOLUTION: This pulse generating circuit is constituted so that a word read-out from a memory 25 may be outputted into a registor 37 which is an address reverser. The resistor 37 read-outs the address in a direction opposite to the one written, and read-outs an electrical condition signal of high level on a read-out bus 39. The resistor 37 is connected with a comparator 41, and the comparator 41 transmits a control signal by comparing a binary comparison value predetermined for a binary value expressed with a transmitted address signal to make the control signal act on a multiplexer 51. The multiplexer 51 loads a resistor 45 with a numeric value according to a control signal value. It is thus possible to obtain the waveform of a pulse duration modulation signal with a memory word address in the memory 25, distributed in a harmonic way and kept in its permissible allowance.
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Inventors:
MARUKO BIRUJAN
MAKISHIMU TESHE
MAKISHIMU TESHE
Application Number:
JP11495797A
Publication Date:
April 19, 1999
Filing Date:
March 28, 1997
Export Citation:
Assignee:
ESU TEE MIKUROEREKUTORONIKUSU SA
International Classes:
H02P25/02; H02P27/08; H03K7/08; (IPC1-7): H02M7/48; H02M7/5387; H02P7/63; H03K7/08
Attorney, Agent or Firm:
Takashi Koshiba