PURPOSE: To generate a pulse accurately at a high speed even when a circuit is constituted of a device of a next stage with a small drive power by constitut ing this circuit with the arithmetic operation between the output of a master section of one FF circuit and the output of a slave section of other FF circuit in this invention.

CONSTITUTION: An arithmetic operation (NOR) for forming a load pulse is implemented between the output signal B of a master FF 1 in a 1st frequency divider 10 and the output signal D of a 2nd frequency divider 20. Since the output signal B of the FF 1 is deviated by only a half clock from the output signal C of a slave FF 2, a correct load pulse signal is generated from NOR circuits B, D. In such constitution, the waveform of the output of a load pulse generating circuit is decided. Number of fan-out of the FF 1 is 2 and small. Since the number of the fan-outs of both FFs is 2 to be symmetry, the circuit operation is stable and the toggle frequency of the FF itself (highest operating frequency in a frequency divider) is improved, then high speed operation is attained.